february 1994 revised april 1999 74lcx646 low voltage octal transceiver/register with 5v tolerant inputs and outputs ? 1999 fairchild semiconductor corporation ds011997.prf www.fairchildsemi.com 74lcx646 low voltage octal transceiver/register with 5v tolerant inputs and outputs general description the lcx646 consists of registered bus transceiver circuits, d-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. data on the a or b bus will be loaded into the respective registers on the low-to-high transition of the appropriate pin (cpab or cpba)(see functional description). the lcx646 is designed for low voltage (2.5v or 3.3v) v cc applications with capability of interfacing to a 5v signal environment. the lcx646 is fabricated with an advanced cmos tech- nology to achieve high speed operation while maintaining cmos low power dissipation. features n 5v tolerant inputs and outputs n 2.3v - 3.6v v cc specifications provided n 7.0 ns t pd max (v cc = 3.3v), 10 m a i cc max n power down high impedance inputs and outputs n supports live insertion/withdrawal (note 1) n 24 ma output drive (v cc = 3.0v) n implements patented noise/emi reduction circuitry n latch-up performance exceeds 500 ma n esd performance: human body model > 2000v machine model > 200v note 1: to ensure the high-impedance state during power up or down, oe should be tied to v cc through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. ordering code: devices also available in tape and reel. specify by appending the suffix letter x to the ordering code. connection diagram pin descriptions order number package number package description 74lcx646wm m24b 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide 74lcx646msa msa24 24-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide 74lcx646mtc mtc24 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description a 0 Ca 7 data register a inputs data register a outputs b 0 Cb 7 data register b inputs data register b outputs cpab, cpba clock pulse inputs sab, sba transmit/receive inputs oe output enable input dir direction control input
www.fairchildsemi.com 2 74lcx646 logic symbols ieee/iec truth table (note 2) h = high voltage level l = low voltage level x = immaterial = low-to-high transition note 2: the data output functions may be enabled or disabled by various signals at the oe and dir inputs. data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the appropriate clock inputs. inputs data i/o function oe dir cpab cpba sab sba a 0 Ca 7 b 0 Cb 7 h x h or l h or l x x isolation hx x x x input input clock a n data into a register hxx x x clock b n data into b register lhxxlx a n to b n real time (transparent mode) lh x l x input output clock a n data into a register l h h or l x h x a register to b n (stored mode) lh x h x clock a n data into a register and output to b n l lxxxl b n to a n real time (transparent mode) llx x l output input clock b n data into b register l l x h or l x h b register to a n (stored mode) llx x h clock b n data into b register and output to a n
3 www.fairchildsemi.com 74lcx646 functional description in the transceiver mode, data present at the high imped- ance port may be stored in either the a or b register or both. the select (sab, sba) controls can multiplex stored and real-time. the examples shown below demonstrate the four fundamental bus-management functions that can be performed. the direction control (dir) determines which bus will receive data when oe is low. in the isolation mode (oe high), a data may be stored in one register and/or b data may be stored in the other register. when an output func- tion is disabled, the input function is still enabled and may be used to store and transmit data. only one of the two busses, a or b, may be driven at a time. real-time transfer bus b to bus a real-time transfer bus a to bus b transfer storage data to a or b storage oe dir cpab cpba sab sba ll x x x l oe dir cpab cpba sab sba lhxxlx oe dir cpab cpba sab sba llxh or lx h lhh or lxhx oe dir cpab cpba sab sba lh xlx llx xl hx xxx hxx xx
www.fairchildsemi.com 4 74lcx646 logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate pro pagation delays.
5 www.fairchildsemi.com 74lcx646 absolute maximum ratings (note 3) recommended operating conditions (note 5) note 3: the absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maxi m um ratings. the recom- mended operating conditions table will define the conditions for actual device operation. note 4: i o absolute maximum rating must be observed. note 5: unused inputs or i/os must be held high or low. they may not float. dc electrical characteristics symbol parameter value conditions units v cc supply voltage - 0.5 to + 7.0 v v i dc input voltage - 0.5 to + 7.0 v v o dc output voltage - 0.5 to + 7.0 output in 3-state v - 0.5 to v cc + 0.5 output in high or low state (note 4) i ik dc input diode current - 50 v i < gnd ma i ok dc output diode current - 50 v o < gnd ma + 50 v o > v cc i o dc output source/sink current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per ground pin 100 ma t stg storage temperature - 65 to + 150 c symbol parameter min max units v cc supply voltage operating 2.0 3.6 v data retention 1.5 3.6 v i input voltage 05.5v v o output voltage high or low state 0 v cc v 3-state 0 5.5 i oh /i ol output current v cc = 3.0v - 3.6v 24 ma v cc = 2.7v - 3.0v 12 v cc = 2.3v - 2.7v 8 t a free-air operating temperature - 40 85 c d t/ d v input edge rate, v in = 0.8v - 2.0v, v cc = 3.0v 0 10 ns/v symbol parameter conditions v cc t a = - 40 c to + 85 c units (v) min max v ih high level input voltage 2.3 - 2.7 1.7 v 2.7 - 3.6 2.0 v il low level input voltage 2.3 - 2.7 0.7 v 2.7 - 3.6 0.8 v oh high level output voltage i oh = - 100 m a2.3 - 3.6 v cc - 0.2 v i oh = - 8 ma 2.3 1.8 i oh = - 12 ma 2.7 2.2 i oh = - 18 ma 3.0 2.4 i oh = - 24 ma 3.0 2.2 v ol low level output voltage i ol = 100 m a2.3 - 3.6 0.2 v i ol = 8 ma 2.3 0.6 i ol = 12 ma 2.7 0.4 i ol = 16 ma 3.0 0.4 i ol = 24 ma 3.0 0.55 i i input leakage current 0 v i 5.5v 2.3 - 3.6 5.0 m a i oz 3-state i/o leakage 0 v o 5.5v 2.3 - 3.6 5.0 m a v i = v ih or v il i off power-off leakage current v i or v o = 5.5v 0 10 m a
www.fairchildsemi.com 6 74lcx646 dc electrical characteristics (continued) note 6: outputs disabled or 3-state only. ac electrical characteristics note 7: skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of th e same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). dynamic switching characteristics capacitance symbol parameter conditions v cc t a = - 40 c to + 85 c units (v) min max i cc quiescent supply current v i = v cc or gnd 2.3 - 3.6 10 m a 3.6v v i , v o 5.5v (note 6) 2.3 - 3.6 10 d i cc increase in i cc per input v ih = v cc - 0.6v 2.3 - 3.6 500 m a symbol parameter t a = - 40 c to + 85 c, r l = 500 w units v cc = 3.3v 0.3v v cc = 2.7v v cc = 2.5v 0.2v c l = 50 pf c l = 50 pf c l = 30 pf min max min max min max f max maximum clock frequency 150 mhz t phl propagation delay 1.5 7.0 1.5 8.0 1.5 8.4 ns t plh bus to bus 1.5 7.0 1.5 8.0 1.5 8.4 t phl propagation delay 1.5 8.5 1.5 9.5 1.5 10.5 ns t plh clock to bus 1.5 8.5 1.5 9.5 1.5 10.5 t phl propagation delay 1.5 8.5 1.5 9.5 1.5 10.5 ns t plh select to bus 1.5 8.5 1.5 9.5 1.5 10.5 t pzl output enable time 1.5 8.5 1.5 9.5 1.5 10.5 ns t pzh 1.5 8.5 1.5 9.5 1.5 10.5 t plz output disable time 1.5 8.5 1.5 9.5 1.5 10.5 ns t phz 1.5 8.5 1.5 9.5 1.5 10.5 t s setup time 2.5 2.5 4.0 ns t h hold time 1.5 1.5 2.0 ns t w pulse width 3.3 3.3 4.0 ns t oshl output to output skew 1.0 ns t oslh (note 7) 1.0 symbol parameter conditions v cc (v) t a = 25 c units typ ical v olp quiet output dynamic peak v ol c l = 50 pf, v ih = 3.3v, v il = 0v 3.3 0.8 v c l = 30 pf, v ih = 2.5v, v il = 0v 2.5 0.6 v olv quiet output dynamic valley v ol c l = 50 pf, v ih = 3.3v, v il = 0v 3.3 - 0.8 v c l = 30 pf, v ih = 2.5v, v il = 0v 2.5 - 0.6 symbol parameter conditions typical units c in input capacitance v cc = open, v i = 0v or v cc 7pf c i/o input/output capacitance v cc = 3.3v, v i = 0v or v cc 8pf c pd power dissipation capacitance v cc = 3.3v, v i = 0v or v cc , f = 10 mhz 25 pf
7 www.fairchildsemi.com 74lcx646 ac loading and waveforms generic for lcx family figure 1. ac test circuit (c l includes probe and jig capacitance) waveform for inverting and non-inverting functions propagation delay. pulse width and t rec waveforms 3-state output low enable and disable times for logic 3-state output high enable and disable times for logic setup time, hold time and recovery time for logic t rise and t fall figure 2. waveforms (input characteristics; f =1mhz, t r = t f = 3ns) test switch t plh , t phl open t pzl , t plz 6v at v cc = 3.3 0.3v v cc x 2 at v cc = 2.5 0.2v t pzh ,t phz gnd symbol v cc 3.3v 0.3v 2.7v 2.5v 0.2v v mi 1.5v 1.5v v cc /2 v mo 1.5v 1.5v v cc /2 v x v ol + 0.3v v ol + 0.3v v ol + 0.15v v y v oh - 0.3v v oh - 0.3v v oh - 0.15v
www.fairchildsemi.com 8 74lcx646 schematic diagram generic for lcx family
9 www.fairchildsemi.com 74lcx646 physical dimensions inches (millimeters) unless otherwise noted 24-lead small outline integrated circuit (soic), jedec ms-013, 0.300 wide package number m24b 24-lead shrink small outline package (ssop), eiaj type ii, 5.3mm wide package number msa24
fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. 74lcx646 low voltage octal transceiver/register with 5v tolerant inputs and outputs life support policy fairchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com physical dimensions inches (millimeters) unless otherwise noted (continued) 24-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc24
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